1. Technical Field
Various embodiments relate to a semiconductor circuit, and more particularly, to a semiconductor memory.
2. Related Art
A semiconductor memory is designed to meet a specification of a page size.
In this case, the page size may be defined by the number of bit lines which is simultaneously operated at the time of an active operation of the semiconductor memory.
For example, FIG. 1 illustrates a core structure of a semiconductor memory 10 which is designed to meet a 2 KB page size.
In this case, the core may include a bank which is a memory block.
The bank may be divided into an upper bank BK_UP and a lower bank BK_DN.
When the page size is set to be 2 KB, a column of the bank becomes 2 KB.
In the structure, as one word line WL is activated, the bit lines of 2 KB are simultaneously operated.
As illustrated in FIG. 2, describing an internal structure of the core of FIG. 1, four segment input/output lines SIO are each connected to upper/lower portions of each unit memory block, that is, each mat MAT.
The segment input/output lines SIO are connected to local input/output lines LIO through input/output switches IOSW, such that a total of 16 data by 8 data for each mat MAT in the upper bank BK_UP or the lower bank BK_DN are output.
Meanwhile, FIG. 3 illustrates a core structure of a semiconductor memory 20 which is designed to meet a 4 KB page size.
In the structure, as two word lines WL by one in the upper bank BK_UP and the lower bank BK_DN, respectively, are simultaneously activated, bit lines of 4 KB are simultaneously operated.
As illustrated in FIG. 4, describing an internal structure of the core of FIG. 3, two mats MAT share the segment input/output line SIO.
The segment input/output lines SIO are connected to the local input/output lines LIO through the input/output switches IOSW, such that a total of 16 data by 8 data in the upper bank BK_UP or the lower bank BK_DN, respectively, are output.
As described above, the semiconductor memory in accordance with the related art has different core structures for each page size.
Therefore, the related art has a problem in that the semiconductor memory is manufactured as a separate chip depending on the page size.